#Modelsim altera tutoral testbench how to
#Modelsim altera tutoral testbench series

HEX2LED Converts 4-bit values of Ones and Tens to 7-segment LED format.

1-2 Xilinx Development SystemР”Р€ CNT60 A counter that outputs Ones and Tens digits as 4-bit binary values. Optionally implemented using either the tenths.vhd (tenths.v) file or a LogiBLOX macro.

TENTHS A 10-bit counter which outputs the Tenths digit as 10- bit value. STWATCH A state machine that controls starting, stopping, and clearing the counters. DIVIDER A clock divider which divides the 36 KHz clock input to 17.5 Hz for internal use. The top level of the Watch design consists of the following functional blocks. TENTHSOUT 10-bit bus which represents the tenths-digit of the stopwatch value. ONESOUT Similar to TENSOUT bus above, but represents the one-digit of the stopwatch value.

#Modelsim altera tutoral testbench series

This is viewable on the 7-segment LCD display of the XCR series demo board. Outputs TENSOUT 7-bit bus which represents the tens-digit of the stopwatch value. A 36 KHz clock is used on XCR demo board. RESET Forces the signals TENSOUT and ONESOUT to be 00 after the stopwatch has been stopped. This is an active-low signal that must be depressed then released to start or stop the counting. Inputs STRTSTOP The start/stop button of the stopwatch. The Watch design inputs, outputs, and modules are summarized below. Xilinx CPLDs do not have an on chip oscillator, and most of the differences in the tutorials are due to the use of an external system clock for the CPLD. There is a companion Watch tutorial for Xilinx FPGAs, which have an on chip oscillator. There are two external inputs and three external outputs in the completed design. Synopsys Design Compiler - FPGA Compiler Tutorial for CPLDs 1-1Р”Сћ Synopsys Design Compiler - FPGA Compiler Tutorial for CPLDs The Watch design is a counter that counts up from 0 to 59, then resets to zero, and starts over. The tutorial assumes that you have a working knowledge of VHDL and/or Verilog. Design Description Before Beginning the Tutorial Tutorial Installation Design Flow Creating the tenths LogiBLOX component for the XC9500 RTL Simulation Synthesizing the Design Using Synopsys Implementing the Watch Design XC9500/XL/XV Timing simulation XCR Timing simulation Throughout this tutorial, the design is referred to as Watch which is a design for a runner s stop watch.

This tutorial contains the following sections. It guides you through a typical CPLD HDL-based design procedure using a design of a runner s stopwatch called Watch.

#Modelsim altera tutoral testbench how to

1 Chapter 1 Synopsys Design Compiler/FPGA Compiler/ ModelSim Tutorial for CPLDs Design Description This tutorial shows you how to use Synopsys Design Compiler/ FPGA Compiler (VHDL/Verilog) for compiling XC9500/XL/XV and Xilinx CoolRunner (XCR) CPLD designs, and Model Technology s ModelSim for simulation.